When constructing a digital data processor it is often the case that a plurality of different clock frequencies are required for different components or sub-systems. As an example, a system bus may interconnect a plurality of printed circuit cards or modules. The system bus will often include one or more signal lines that convey a synchronizing clock frequency. If a particular circuit card or module requires one of the clock frequencies, it is a relatively simple operation to input the desired clock frequency from the system bus, buffer same, and distribute the buffered clock to the appropriate component(s). If some sub-multiple of the clock frequency is required, it is also a relatively simple operation to provide one or more flip/flops to divide the input clock frequency to the desired frequency. Frequency division also typically inherently provides a symmetrical (50% duty cycle) waveform.
However, a problem is encountered when some multiple of the input clock frequency is required.
One approach is to provide a separate oscillator on the circuit card or module to provide the desired higher frequency. However, clock oscillators are generally expensive, and may require a substantial amount of printed circuit board area. Furthermore, the output frequency signal of the separate clock oscillator will generally be asynchronous to the system bus clock. As a result, additional synchronizing circuitry may be required if the local, higher frequency clock is required to have some predetermined phase relationship to the system bus clock.